For conventional manufacturing processes of a TFTLCD, a tri-layer process and a back channel etch (BCE) process are main streams for forming the TFT matrix. Compared to a BCE structure, a tri-layer structure additionally includes an top nitride over the semiconductor layer as a etch stopper so that the etching step for defining a source/drain and channel region can be well controlled. Accordingly, the thickness of the active layer can be made to be thinner in the tri-layer structure than in the BCE structure, which is advantageous for the stability of resulting devices and performance in mass production. However, the provision of the additional etch stopper layer needs an additional masking step, thereby making the tri-layer process relatively complicated.
Conventionally, six to nine masking steps are required for either a BCE process or a tri-layer process. After the formation of the TFT matrix, a step of providing a black matrix around each pixel electrode region is generally required to improve the performance of the LCD. The provision of the black matrix after the process, however, will have difficulty in alignment.
On the other hand, the count of photo-masking and lithography steps directly affects not only the production cost but also the manufacturing time. Moreover, for each photo-masking and lithography step, the risks of mis-alignment and contamination may be involved so as to affect the production yield. Therefore, many efforts have been made to improve the conventional processes to reduce masking steps.
For example, for a BCE structure, U.S. Pat. Nos. 5,346,833 and 5,478,766 issued to Wu and Park et al., respectively, disclose 3 and/or 4 -mask processes for making a TFTLCD, which are incorporated herein for reference. By the way, it is to be noted that the 3-mask process for each of Wu and Park et al. does not include the step of forming and patterning of a passivation layer. If a passivation layer is required to assure of satisfactory reliability, the count of photo-masking and lithography steps should be four. Further, Wu and Park et al. use an ITO layer, which is integrally formed with the ITO pixel electrode, as the connection line between the TFT unit and the data line so that the area of the TFTLCD is limited due to the high resistivity of ITO.
As for the tri-layer structure, a conventional 6-mask process is illustrated as follows with reference to FIGS. 1A.about.1G which are cross-sectional views of intermediate structures at different stages. The conventional process includes steps of:
i) applying a first conductive layer onto a glass substrate 10, and using a first photo-masking and lithography procedure to pattern and etch the first conductive layer to form an active region 11 consisting of a scan line and a gate electrode of a TFT unit, as shown in FIG. 1A; PA1 ii) sequentially forming tri-layers including an insulation layer 121, a semiconductor layer 122 and an etch stopper layer 123, and a photoresist 124 on the resulting structure of FIG. 1A, as shown in FIG. 1B. PA1 iii) using a second photo-masking and lithography procedure to pattern and etch the etch stopper layer 123 to form an etch stopper 13 which have a shape similar to the shape of the gate electrode, as shown in FIG. 1C; PA1 iv) using a third photo-masking and lithography procedure to pattern and etch the semiconductor layer 122 to form a channel structure 14, as shown in FIG. 1D; PA1 v) sequentially applying a doped semiconductor layer and a second conductive layer on the resulting structure of FIG. 1D, and using a fourth photo-masking and lithography procedure to pattern and etch them to form source/drain regions 15 and data and connection lines 16, as shown in FIG. 1E; PA1 vi) applying a passivation layer 17 on the resulting structure of FIG. 1E, and using a fifth photo-masking and lithography procedure to pattern and etch the passivation layer 17 to create tape automated bonding (TAB) openings (not shown), and create a contact window 18, as shown in FIG. 1F; and PA1 vii) applying a transparent electrode layer on the resulting structure of FIG. 1F, and using a sixth photo-masking and lithography procedure to pattern and etch the transparent electrode layer to form a pixel electrode 19, as shown in FIG. 1G.
Six masking steps, however, are still too complicated.